MIPS R10000 Uses Decoupled Architecture: 10/24/94

Not to be left out in the move to the next generation of RISC, MIPS Technologies (MTI) unveiled the design of the R10000, also known as T5. As the spiritual successor to the R4000, the new design will be the basis of high-end MIPS processors for some time, at least until 1997. By swapping superpipelining for an aggressively out-oforder superscalar design, the R10000 has the potential to deliver high performance throughout that period. The new processor uses deep queues decouple the instruction fetch logic from the execution units. Instructions that are ready to execute can jump ahead of those waiting for operands, increasing the utilization of the execution units. This technique, known as out-of-order execution, has been used in PowerPC processors for some time (see 081402.PDF ), but the new MIPS design is the most aggressive implementation yet, allowing more instructions to be queued than any of its competitors. MIPS R10000 Uses De